1. Field of the Invention
The present invention relates to a placement method, and more particularly, to a placement method for decoupling capacitors in a semiconductor circuit and a semiconductor structure using the same.
2. Description of the Related Art
A current trend in semiconductor design, particularly for application specific integrated circuits (ASICs) and advanced/complex semiconductor integrated circuit devices, such as microprocessors, is to lower operating power, thus trend driving power supply and device threshold voltages to lower levels. Another trend emphasizing the need for decoupling is that voltage scaling has lagged behind area/capacitance scaling. As the supply voltage (VCC) and device threshold voltage (Vt) drop, the ratio of noise voltage to Vt and VCC increase, since noise levels do not scale down at the same rate as Vt and VCC. Consequently, sensitivity to noise in these types of semiconductor integrated circuit devices increase. In order to minimize noise effects, decoupling capacitors are often needed in VLSI circuits.
Capacitance per unit area provided by conventional capacitance cells, however, is low due to capacitance cell layout style and layout rule.